The present invention relates to a storage apparatus and more specifically to a technique effectively applied to a process required at a time of occurrence of soft errors of memory cells in a microprocessor (CPU) owing to disturbances such as a (alpha) rays, neutrons, and electromagnetic waves.
Conventionally, in a storage apparatus that supplies memory areas to hosts such as servers, a host interface control unit that controls data transfer with hosts has been controlled by a microprocessor (for example, see Japanese Patent Laid-open No. 2003-58323).
Recently, as LSIs are miniaturized, the incidence of soft errors that occur in a primary cache or general purpose register built in the microprocessor of the host interface control due to disturbances such as a (alpha) rays, neutrons, and electromagnetic waves has become high.
When the soft errors occur in the microprocessor, control from the microprocessor is impossible and the host interface control unit becomes inoperative. Then, on a side of the host, an I/O access becomes time over and this is recognized as failure of the host interface control unit in which the soft errors have occurred, so that its path is blocked and a change of the path is made.